Complementary metal-oxide semiconductor (CMOS) image sensors are gaining in popularity over traditional charged-coupled devices (CCDs). A CMOS image sensor typically comprises an array of pixels, which utilize light-sensitive CMOS circuitry to convert photons into electrons. The light-sensitive CMOS circuitry of a pixel typically comprises a photo-diode formed in a silicon substrate. As the photo-diode is exposed to light, an electrical charge is induced in the photo-diode. Each pixel may generate electrons proportional to the amount of light that falls on the pixel when light is incident on the pixel from a subject scene. The electrons are converted into a voltage signal and further transformed into a digital signal.
A CMOS image sensor, which may be referred as a CMOS sensor, may comprise a plurality of dielectric layers and interconnect layers formed on the substrate, connecting the photo diodes in the substrate to peripheral circuitry. The side having the dielectric layers and interconnect layers is commonly referred to as a front side, while the side having the substrate is referred to as a backside. Depending on the light path difference, CMOS image sensors can be classified as front-side illuminated (FSI) image sensors and back-side illuminated (BSI) sensors.
In an FSI image sensor, light from the subject scene is incident on the front side of the CMOS image sensor, passes through dielectric layers and interconnect layers, and falls on the photo diode. In contrast, in a BSI image sensor, light is incident on the backside of the CMOS image sensor without the obstructions from the dielectric layers and interconnect layers. As a result, light can hit the photo diode through a direct path. Such a direct path helps to increase the number of photons converted into electrons, which makes the BSI CMOS sensor more sensitive to the light source.
CMOS sensors are becoming smaller and smaller, due to the continuous reductions of the sizes of the components (i.e., transistors, diodes, resistors, capacitors, etc.), therefore requiring smaller packages. Some smaller types of packages include quad flat pack (QFP), pin grid array (PGA), ball grid array (BGA), flip chips (FC), three dimensional integrated circuits (3DIC), wafer level packages (WLP), wafer-level chip scale packages (WLCSP), and package on package (PoP) devices. These package technologies may be used to achieve a high density required image sensor applications, or other sensor applications.
In a typical packaging process, interconnect structures are formed on metallization layers of the sensor, followed by the formation of contact pads or bond pads to establish electrical contacts between the sensor device and the substrate or lead frame of the package. Conventional bond pads and contact pads may be formed through the backside of the image sensors on the inter-layer dielectric layer and metal layers, which may have a thin support for the package. So formed bond pads may peel during or after bonding due to the fact that the bond pad strength is not strong enough. Methods and systems are needed to strengthen the bond pad support and improve the bonding.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.